structure Sparkle.Core.Sim.Verilator.PortSpec : Type

One input port: name (matches the .sv port) and bit-width. The width drives the C++ type chosen for the jit_set_input switch case (uint8_t, uint16_t, uint32_t, or uint64_t).

• name : String
• width : Nat

def Sparkle.Core.Sim.Verilator.instReprPortSpec.repr : PortSpec → Nat → Std.Format

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instance Sparkle.Core.Sim.Verilator.instReprPortSpec : Repr PortSpec

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• Sparkle.Core.Sim.Verilator.instReprPortSpec = { reprPrec := Sparkle.Core.Sim.Verilator.instReprPortSpec.repr }

def Sparkle.Core.Sim.Verilator.instInhabitedPortSpec.default : PortSpec

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• Sparkle.Core.Sim.Verilator.instInhabitedPortSpec.default = { name := default, width := default }

instance Sparkle.Core.Sim.Verilator.instInhabitedPortSpec : Inhabited PortSpec

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• Sparkle.Core.Sim.Verilator.instInhabitedPortSpec = { default := Sparkle.Core.Sim.Verilator.instInhabitedPortSpec.default }

structure Sparkle.Core.Sim.Verilator.Simulator : Type

Verilator simulator state. Just a JITHandle because the Verilator-backed .so exposes the JIT C ABI.

• handle : JIT.JITHandle

def Sparkle.Core.Sim.Verilator.of (svPath top : String) (inputs outputs : List PortSpec) (objDir : String := "/tmp/sparkle_verilator") : IO Simulator

Build a Verilator-backed .so from a Sparkle-generated .sv, then load it via the existing JIT FFI.

• svPath — path to a .sv written by, e.g., Sparkle.Backend.Verilog.writeVerilogFile.
• top — top-module name (matches what's in the .sv).
• inputs / outputs — port lists excluding clk / rst (matching the JIT's jit_set_input / jit_get_output indexing).
• objDir — temp directory for Verilator artefacts.

Returns a Simulator whose handle is opened against the just-built .so.

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instance Sparkle.Core.Sim.Verilator.instSimSimulatorListProdUInt32UInt64ForallIO : Sim Simulator (List (UInt32 × UInt64)) (UInt32 → IO UInt64)

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