Documentation

Sparkle.Core.JIT

Opaque handle to a loaded JIT shared library

@[extern sparkle_jit_load]

Load a compiled JIT shared library (.dylib/.so)

@[extern sparkle_jit_eval]

Evaluate combinational logic (compute next state)

@[extern sparkle_jit_tick]

Advance clock (apply next state to registers)

@[extern sparkle_jit_eval_tick]

Fused eval+tick: evaluate combinational logic and advance clock in one call. Register next-state values are kept as local variables instead of class members, eliminating ~260 intermediate memory operations per cycle.

@[extern sparkle_jit_reset]

Reset all registers to initial values

@[extern sparkle_jit_destroy]

Destroy the simulation instance (also runs automatically on finalize)

@[extern sparkle_jit_set_input]
opaque Sparkle.Core.JIT.JIT.setInput (h : JITHandle) (portIdx : UInt32) (value : UInt64) :

Set an input port by index

@[extern sparkle_jit_get_output]

Get an output port value by index

@[extern sparkle_jit_get_wire]

Get an internal wire value by index (gen* named wires)

@[extern sparkle_jit_set_mem]
opaque Sparkle.Core.JIT.JIT.setMem (h : JITHandle) (memIdx addr data : UInt32) :

Set a memory word by memory index and address

@[extern sparkle_jit_get_mem]
opaque Sparkle.Core.JIT.JIT.getMem (h : JITHandle) (memIdx addr : UInt32) :

Get a memory word by memory index and address

@[extern sparkle_jit_memset_word]
opaque Sparkle.Core.JIT.JIT.memsetWord (h : JITHandle) (memIdx addr val count : UInt32) :

Fill a range of memory words with a value (bulk write)

@[extern sparkle_jit_snapshot]

Take a full snapshot of the simulation state (registers + memories). Returns an opaque pointer (as UInt64) that can be passed to restore/freeSnapshot.

@[extern sparkle_jit_restore]

Restore simulation state from a snapshot taken by JIT.snapshot.

@[extern sparkle_jit_free_snapshot]

Free a snapshot created by JIT.snapshot. Must be called to avoid memory leaks.

@[extern sparkle_jit_wire_name]

Get the name of a wire by index (for discovery)

@[extern sparkle_jit_num_wires]

Get the total number of observable wires

Find a wire index by name, returns none if not found

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    @[extern sparkle_jit_set_reg]
    opaque Sparkle.Core.JIT.JIT.setReg (h : JITHandle) (regIdx : UInt32) (value : UInt64) :

    Set a register value by index (writes current state, not _next)

    @[extern sparkle_jit_get_reg]

    Get a register value by index

    @[extern sparkle_jit_reg_name]

    Get the name of a register by index (for discovery)

    @[extern sparkle_jit_num_regs]

    Get the total number of registers

    Find a register index by name, returns none if not found

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      @[extern sparkle_jit_run_cdc]
      opaque Sparkle.Core.JIT.JIT.runCDC (handleA handleB : JITHandle) (cyclesA cyclesB : UInt64) (outPortA inPortB : UInt32) :

      Run two JIT domains connected via a lock-free SPSC queue (CDC).

      Domain A (producer) runs cyclesA eval_tick cycles, sending output port values to Domain B via the queue. Domain B (consumer) runs cyclesB eval_tick cycles, receiving values and applying them to its input port. Timestamp inversions trigger automatic rollback via snapshot/restore.

      Returns (messagesSent, messagesReceived, rollbackCount).

      def Sparkle.Core.JIT.JIT.compile (cppPath : String) (cacheDir : String := ".lake/build/jit_cache") :

      Compile a JIT .c (or legacy .cpp) source file to a shared library, with hash-based caching.

      The CSim backend emits pure C — we use cc and -std=c11, and drop libstdc++/libgcc static-linking entirely (the .so has no C++ dependency). We still pin the JIT .so's runtime linker to the host libc (Issue #70) as defence in depth.

      The input path's extension is accepted as .c, .cpp, or .cc for backward compatibility with existing callers that have historical _jit.c literal paths; the file contents are pure C either way.

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        Compile and load a JIT module in one step

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