Documentation

Sparkle.IR.Optimize

@[reducible, inline]

O(1) lookup maps built from module data

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    Build a name → defining-expression map from assign statements

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      Build name → bit-width map from module ports and wires

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        Infer the bit-width of an expression

        partial def Sparkle.IR.Optimize.resolveSliceOfConcatAux (remaining : List (AST.Expr × Nat)) (hiEdge sliceHi sliceLo : Nat) :

        Try to resolve a slice of a concat to a direct reference or narrower slice.

        For concat [a(wa), b(wb), c(wc), ...] with total width T:

        • a occupies [T-1 : T-wa]
        • b occupies [T-wa-1 : T-wa-wb]
        • etc. (MSB-first layout, same as Verilog {a, b, c, ...})

        Returns the replacement if the slice maps entirely within one arg.

        def Sparkle.IR.Optimize.resolveSliceOfConcat (args : List AST.Expr) (widths : List Nat) (sliceHi sliceLo : Nat) :
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          partial def Sparkle.IR.Optimize.resolveSlice (dm : DefMap) (wm : WidthMap) (name : String) (hi lo fuel : Nat) :

          Resolve a slice of a named wire through the defMap, recursively following:

          1. Ref aliases: X = Y → slice(Y, hi, lo)
          2. Slice chains: X = Y[h:l] → slice(Y, l+hi, l+lo)
          3. Concat args: X = {a, b} → a (if slice matches exactly) Depth-limited to prevent infinite recursion on malformed IR.

          Fold constant expressions

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            Optimize a single expression by resolving slice chains, folding constants, and propagating constant-assigned wires.

            Collect all reference names from an expression.

            Count uses of each wire across all statements

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              Optimize a single statement's expressions

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                partial def Sparkle.IR.Optimize.substituteExpr (dm : DefMap) (inlinable : Std.HashMap String Bool) (fuel : Nat) :

                Recursively substitute inlinable references with their defining expressions

                Inline single-use wires: replace references with their defining expressions and remove the now-dead assign statements.

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                  Propagate constant and simple-ref assignments into all uses. x = const → replace all refs to x with const x = y → replace all refs to x with y (alias elimination) This runs even for gen (JIT-observable) wires since they're just aliases.

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                    Filter zero-bit elements out of an Expr tree.

                    lowerExpr / runCircuitH-style elaborators can produce IR nodes that thread a bitVector 0 "empty payload" through .concat and .slice chains — for instance bundle2 X (Signal.pure ()) lowers to .concat [X, <0-bit ref>], and the matching Signal.map Prod.fst lowers to a slice that discards the 0-bit tail.

                    Emitting these into SystemVerilog produces invalid constructs like assign x = 0'd0; (a zero-width literal is not legal SV). This pass rewrites the IR so that:

                    • .const v 0 is dropped from .concat arg lists;
                    • .concat [x] (after dropping zero-bit args) collapses to the single remaining arg;
                    • .concat [] collapses to a 1-bit zero placeholder (should be unreachable in practice — pruned later by DCE);
                    • .slice e hi lo where hi - lo + 1 == 0 is rewritten to a 0-bit constant (later dropped at the use site).

                    Sub-expressions are rewritten recursively.

                    Drop Stmt.assign whose LHS has zero width — these only exist as leftover bookkeeping from 0-bit IR construction (see eliminateZeroBitInExpr). Other Stmt kinds are kept as is.

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                      Run the 0-bit elimination pass over a module's body and wire list.

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                        Optimize a module: strip zero-bit shapes, eliminate concat/slice chains, then remove dead code.

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                          Optimize all modules in a design

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