#showDiagram <ident> — synthesise the named definition and
render the resulting top-level module as an inline SVG block
diagram.
def dff (d : Signal defaultDomain (BitVec 1))
: Signal defaultDomain (BitVec 1) :=
circuit do
let q ← Signal.reg 0#1
q <~ d
return q
#showDiagram dff
No need to spell out the IR by hand: the same elaborator
that powers #synthesizeVerilog produces the IR.AST.Module,
fromModule lifts it into a Diagram, and the renderer
paints it.
Hierarchical designs (multiple @[hardware_module] children)
only show the top module here; use #showDesign for the
full picture.
Equations
- One or more equations did not get rendered due to their size.
Instances For
#showDesign <ident> — synthesise the named definition and
render every module in the resulting Design (parent +
every transitive @[hardware_module] child). Each module
is emitted as its own SVG marker, so JupyterLab shows them
stacked vertically in the cell output.
Equations
- One or more equations did not get rendered due to their size.