Documentation

Sparkle.Core.Domain

Domain Module #

Clock domain configuration for Sparkle HDL.

Purpose #

This module defines clock domains, which specify timing and reset behavior for hardware signals. Each domain has:

Type Safety #

Signals are tagged with their domain at the type level (Signal d α), preventing accidental mixing of signals from different clock domains.

Usage #

Define a custom clock domain:

def FastClock : DomainConfig where
  period := 5000        -- 5ns period (200MHz)
  activeEdge := .rising
  resetKind := .synchronous

Most designs use the default Domain:

def myCircuit : Signal Domain (BitVec 16) := do
  -- Your circuit here
  ...

Multi-Clock Designs #

For designs with multiple clock domains, create separate domain configurations and use type-level tracking to ensure safety:

def Domain100MHz : DomainConfig where
  period := 10000       -- 10ns (100MHz)
  activeEdge := .rising
  resetKind := .synchronous

def Domain50MHz : DomainConfig where
  period := 20000       -- 20ns (50MHz)
  activeEdge := .rising
  resetKind := .synchronous

-- These cannot be mixed due to type safety!
def fast : Signal Domain100MHz (BitVec 8) := ...
def slow : Signal Domain50MHz (BitVec 8) := ...

See also: Sparkle.Core.Signal for signal operations.

@[reducible, inline]

ResetKind is defined in Sparkle.IR.Type so the IR layer can reference it without importing Core/Domain.lean. We alias it as Sparkle.Core.Domain.ResetKind for back-compat with user code that already qualifies it that way.

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    Active edge of a clock signal

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        Domain configuration specifying timing and reset behavior.

        • period: Clock period in picoseconds (e.g., 10000 for 100MHz)
        • activeEdge: Whether to trigger on rising or falling edge
        • resetKind: Synchronous or asynchronous reset
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                Clock signal wrapper carrying domain information. The domain parameter ensures type-safe separation of different clock domains.

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                    Reset signal wrapper carrying domain information. Reset must belong to the same domain as the clock it synchronizes with.

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                        Enable signal wrapper carrying domain information. Enable controls whether registers in a domain are active.

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                            Default domain configuration: 100MHz, rising edge, synchronous reset

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