def Sparkle.Backend.Verilog.sanitizeName (name : String) : String

Sanitize a name to be a valid Verilog identifier

Equations

• Sparkle.Backend.Verilog.sanitizeName name = ((((name.replace "." "_").replace "-" "_").replace " " "_").replace "'" "_prime").replace "#" ""

partial def Sparkle.Backend.Verilog.emitDimExpr : IR.Type.DimExpr → String

Emit a symbolic hardware dimension as a SystemVerilog constant expression.

def Sparkle.Backend.Verilog.emitType (ty : IR.Type.HWType) : String

Convert HWType to Verilog type declaration

Equations

• Sparkle.Backend.Verilog.emitType Sparkle.IR.Type.HWType.bit = "logic"
• Sparkle.Backend.Verilog.emitType (Sparkle.IR.Type.HWType.bitVector 1) = "logic"
• Sparkle.Backend.Verilog.emitType (Sparkle.IR.Type.HWType.bitVector w) = toString "logic [" ++ toString (w - 1) ++ toString ":0]"
• Sparkle.Backend.Verilog.emitType (Sparkle.IR.Type.HWType.bitVectorDim width) = toString "logic [" ++ toString (Sparkle.Backend.Verilog.emitDimExpr width) ++ toString "-1:0]"
• Sparkle.Backend.Verilog.emitType (Sparkle.IR.Type.HWType.array size elemType) = toString (Sparkle.Backend.Verilog.emitType elemType) ++ toString " [" ++ toString (size - 1) ++ toString ":0]"

def Sparkle.Backend.Verilog.emitOperator (op : IR.AST.Operator) : String

Convert Operator to Verilog operator symbol

Equations

• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.and = "&"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.or = "|"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.xor = "^"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.not = "~"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.add = "+"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.sub = "-"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.mul = "*"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.eq = "=="
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.lt_u = "<"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.lt_s = "<"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.le_u = "<="
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.le_s = "<="
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.gt_u = ">"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.gt_s = ">"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.ge_u = ">="
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.ge_s = ">="
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.shl = "<<"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.shr = ">>"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.asr = ">>>"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.neg = "-"
• Sparkle.Backend.Verilog.emitOperator Sparkle.IR.AST.Operator.mux = "?"

partial def Sparkle.Backend.Verilog.emitExpr (widthOf : String → Option Nat := fun (x : String) => none) (e : IR.AST.Expr) : String

Convert IR expression to Verilog expression. widthOf maps a wire name to its declared bit width (when known), so a full-width / scalar .slice can be elided — Verilog forbids a part-select on a scalar (s[0:0] → "can not select part of scalar").

def Sparkle.Backend.Verilog.emitStmt (stmt : IR.AST.Stmt) (indent : String := " ") (wires : List IR.AST.Port := []) : String

Emit a single statement. The optional wires parameter provides wire declarations for register reset value width lookup.

Equations

• One or more equations did not get rendered due to their size.

def Sparkle.Backend.Verilog.emitPortList (inputs outputs : List IR.AST.Port) : String

Emit port declarations for module header

Equations

• One or more equations did not get rendered due to their size.

def Sparkle.Backend.Verilog.emitWireDecls (wires : List IR.AST.Port) (indent : String := " ") : String

Emit wire declarations

Equations

• One or more equations did not get rendered due to their size.

def Sparkle.Backend.Verilog.emitParameterList (parameters : List IR.AST.Parameter) : String

Emit a SystemVerilog module parameter list.

Equations

• One or more equations did not get rendered due to their size.

def Sparkle.Backend.Verilog.emitModule (m : IR.AST.Module) : String

Emit the full module

Equations

• One or more equations did not get rendered due to their size.

def Sparkle.Backend.Verilog.toVerilog (m : IR.AST.Module) : String

Main entry point: Convert a Module to SystemVerilog

Equations

• Sparkle.Backend.Verilog.toVerilog m = Sparkle.Backend.Verilog.emitModule m

def Sparkle.Backend.Verilog.toVerilogDesign (d : IR.AST.Design) : String

Convert a full Design to SystemVerilog.

Each module is run through the IR optimizer first — exactly as #synthesizeVerilog does before toVerilog (see Sparkle.Compiler.Elab). This is essential, not cosmetic: the optimizer's 0-bit elimination pass strips the degenerate 0-width concat tails that circuit do / Signal.loop bundles leave behind ({reg, <0-bit>}). Without it those tails reach emitConst, which promotes a 0-width literal to 1'd0, widening the concat by one bit so the intermediate wire (sized for the real field) TRUNCATES the real value away — silently freezing the least-significant register of every bundle at its reset value. Hierarchical emission (#writeVerilogDesign) is the only source of the @[hardware_module] submodules, so skipping this here broke every sub-module's last register (e.g. uartRxHW's rxValid).

Equations

• One or more equations did not get rendered due to their size.

def Sparkle.Backend.Verilog.writeVerilogFile (m : IR.AST.Module) (filename : String) : IO Unit

Write module to a file

Equations

• Sparkle.Backend.Verilog.writeVerilogFile m filename = do IO.FS.writeFile { toString := filename } (Sparkle.Backend.Verilog.toVerilog m) IO.println (toString "Generated " ++ toString filename)

def Sparkle.Backend.Verilog.writeVerilogDesignFile (d : IR.AST.Design) (filename : String) : IO Unit

Write a full design to a file

Equations

• One or more equations did not get rendered due to their size.