Combinational-dependency analysis (per module) #
Input ports that output port of m combinationally depends on.
[] means a Moore output (function of registers/constants only).
Equations
- Sparkle.Backend.CudaIntra.combDeps m port = do let deps ← Sparkle.Backend.CudaIntra.combWalk✝ (Sparkle.Backend.CudaIntra.netMapsOf✝ m) (4 * m.body.length + 16) [] port pure deps.eraseDups
Instances For
Top-level structure #
One top-level .inst, with its resolved module and the fused-struct
field name CSim gives it (must match CSim.emitStmt's .inst naming).
- modName : String
- instName : String
- field : String
Sanitised field name inside the top struct.
- mod : IR.AST.Module
- conns : List (String × IR.AST.Expr)
Instances For
Where a connection's value comes from, after chasing top-level const/ref assign chains.
- instOutput (producer : InstInfo) (port : String) : ConnSource
- topInput (port : String) : ConnSource
- imm (value : Int) (width : Nat) : ConnSource
Instances For
Copy / immediate tables #
Emission #
Generate the intra .cu for a whole Design. The file contains the
CSim device code (all modules, host+device qualified), the intra tables +
kernels, AND the batch kernel + host JIT API — one .so serves both
axes. Compile with -rdc=true (cooperative groups).
Equations
- One or more equations did not get rendered due to their size.
Instances For
Like toCudaIntraDesign, but renders an analysis error as a #error
line so a build-time generation failure is loud at nvcc time.
Equations
- One or more equations did not get rendered due to their size.